Electronic devices for differentially driving a load are known.
In the mobile phones segment, the load is represented by the loudspeaker of a mobile phone and the electronic device for differentially driving such a load is typically a Class D amplifier.
In the FIG. 1, a differential output stage 100 of a Class-D amplifier, for differentially driving a load, belonging to the prior art, is shown.
With reference to FIG. 1, input signals INPH-INPL and INNH-INNL, are the outputs of a Pulse Width Modulator (PWM), not shown in the figure, arranged upstream the differential output stage 100 and being included in the Class-D amplifier. The differential output stage 100 is arranged to differentially drive a load schematically represented by a resistor RLOAD and an inductor LLOAD connected in series with one another.
In mobile phone applications or in general in the audio field, the supply voltage VDD of the differential output stage 100 is maintained at a high power level in order to guarantee the needed power to the load.
Typically, the differential output stage 100 comprises an output circuit comprising two switches connected in series with one another, i.e. a PMOS transistor M1PSW and a NMOS transistor M1NSW, respectively, between the first reference potential VDD and the second reference potential GND.
With recent technologies, in which MOS transistors are less able to sustain high power level voltages, a PMOS transistor M1PCASC and a NMOS transistor M1NCASC connected in series in a cascode configuration with the MOS transistor M1PSW and NMOS transistor M1NSW, respectively, have been introduced in the output circuit of the differential output stage 100, in order to reduce VGD (voltage drop between a gate terminal and a drain terminal), VGS (voltage drop between a gate terminal and a source terminal) and VDS (voltage drop between a drain terminal and a source terminal) of any MOS transistor of the output circuit of the differential output stage 100.
In their off state (OFF), the PMOS transistor M1PSW and the NMOS transistor M1NSW are driven on a respective gate terminal with driving voltages DRIVEPSW and DRIVENSW, respectively, having value close to the supply voltage VDD or the ground GND. In their on state (ON), the PMOS transistor M1PSW and the NMOS transistor M1NSW are driven on the respective gate terminal with driving voltages DRIVEPSW and DRIVENSW, respectively, having always the same distance, independently from the supply voltage VDD, from the supply voltage VDD or the ground GND. In a corresponding way, the PMOS transistor M1PCASC and the NMOS transistor M1NCASC have the same distance, independently from the supply voltage VDD, from the supply voltage VDD or the ground GND, so that driving voltages, in the on state of the MOS transistors, always maintain the same distance to the supply voltage VDD (for the PMOS transistors) or to the ground GND (for the NMOS transistors) even if the supply voltage VDD changes.
This is in order to obtain driving voltages which guarantee reliability and maintain a constant VGS voltage in the MOS transistor in the on state. This also implies the reduction of the resistance variation of the MOS transistors present in the output circuit of the differential output stage 100 for improving linearity of the signal on the load also in the case of variation of the supply voltage VDD.
In order to generate the driving voltage DRIVEPSW and DRIVENSW, the differential output stage 100 comprises a driving circuit 110 arranged to provide a current of the Vref/R type that in the differential output stage 100, being Vref a fixed voltage (e.g. 1.6V), flows in resistances correspondent to R1 and R4, respectively, obtaining constant and precise value of driving voltages.
With reference again to FIG. 1, the driving circuit 110 comprising a PMOS transistor M1P and a NMOS transistor M1N having a impedance which is negligible for the current I1 flowing in the PMOS transistor M1P and the current I4 flowing in the NMOS transistor M1N, i.e. the voltage drop on the PMOS transistor M1P and the NMOS transistor M1N of the driving circuit 110 is negligible with respect to the currents I1 and I4. In addition, the level of the input signal INLL and the level of the input signal INLH are compatible with reliability, and are logically coincident.
In view of this, in the case the input signals INPL and INPH are high, the output signal OP of the differential output device 100 is high (close to the supply voltage VDD) and, in the case the input signals INPL and INPH are low, the output signal OP of the differential output stage 100 is low (close to the ground GND).
However, the differential output stage 100 of FIG. 1 has many drawbacks.
In fact, the resistive load RLOAD is usually heavy (e.g. 8 Ohms) and therefore the MOS transistors (M1PSW, M1PCASC, M1NCASC and M1NSW) of the output circuit of the differential output stage 100 are very large (e.g. having a width W=10000-30000 μm) and almost represents the total area of the differential output stage 100 and therefore of the Class-D amplifier.
In addition, despite the dimension, the voltage drop between the drain terminal and the source terminal (VDS) of each MOS transistor of the output circuit of the differential output stage 100 represents a limit for the linearity of the output signal OL on the load. This is due to the fact that the impedance of each MOS transistor of the output circuit of the differential output stage 100 is not constant but changes according to the changes of the drop voltage VDS of each MOS transistor. The drop voltage VDS can change on the basis of the value of the current IL present on the resistive/inductive load.
In this regard, it should be considered the equation of a MOS transistor in the linear zone, as follows:I=k·[(VGS−VT)·VDS−(VDS2)/2]
wherein I is the current flowing in the MOS transistor, K is a constant depending on technology and dimension of the MOS transistor, VGS is the voltage drop between the gate terminal and the source terminal of the MOS transistor, VT is the threshold voltage of the MOS transistor, and VDS is the voltage drop between the drain terminal and the source terminal of the MOS transistor.
The resistance R of the MOS transistor is 1/G, wherein G is the conductance of the MOS transistor, equal to the following equation:G=dI/dVDS=k·[(VGS−VT)−VDS]=k·(VGS−VDS−VT)=k·[(VG−VS)−(VD−VS)−VT]=k·(VGD−VT)
This means that the resistance R of the MOS transistor is constant only in the case the voltage drop VGD (voltage drop between the gate terminal and the drain terminal of the MOS transistor) is fixed, thus in the case the gate voltage VG is fixed while the drain voltage VD changes with the current IL present on the resistive/inductive load, the resistance R of the MOS transistor is not constant.
This condition limits linearity performances of the signal on the resistive/inductive load, mainly in open-loop Class D amplifier applications. It could be possible to improve linearity performances by increasing the dimensions of the MOS transistor of the output circuit of the differential output stage 100, in order to reduce the effect of the variation of the resistance of the MOS transistors (as explained above), but this approach is incompatible with the need to save acceptable area and costs of the differential output stage 100, and then of the Class-D amplifier.